HP KC.32101.DMP Datasheet download pdf (Page 8)

8 Datasheet, Volume 1

4-11 Coordination of Core Power States at the Package Level ..............................................55

4-12 Targeted Memory State Conditions............................................................................60

5-1 Intel

Turbo Boost Technology Package Power Control Settings....................................67

5-2 Configurable TDP Modes ..........................................................................................69

5-3 TDP Specifications ..................................................................................................71

5-4 Junction Temperature Specification ...........................................................................71

5-5 Package Turbo Parameters.......................................................................................72

5-6 Idle Power Specifications .........................................................................................73

6-1 Signal Description Buffer Types ................................................................................81

6-2 Memory Channel A..................................................................................................82

6-3 Memory Channel B..................................................................................................83

6-4 Memory Reference and Compensation .......................................................................84

6-5 Reset and Miscellaneous Signals ...............................................................................84

6-6 PCI Express* Graphics Interface Signals ....................................................................85

6-7 Embedded Display Port Signals.................................................................................85

6-8 Intel

Flexible Display Interface ...............................................................................85

6-9 DMI – Processor to PCH Serial Interface.....................................................................86

6-10 PLL Signals ............................................................................................................86

6-11 TAP Signals............................................................................................................86

6-12 Error and Thermal Protection....................................................................................87

6-13 Power Sequencing ..................................................................................................88

6-14 Processor Power Signals ..........................................................................................89

6-15 Sense Signals ........................................................................................................89

6-16 Ground and NCTF ...................................................................................................90

6-17 Processor Internal Pull Up/Pull Down .........................................................................90

7-1 IMVP7 Voltage Identification Definition ......................................................................92

7-2 VCCSA_VID Configuration........................................................................................95

7-3 Signal Groups1.......................................................................................................96

7-4 Storage Condition Ratings........................................................................................98

7-5 Processor Core (V

) Active and Idle Mode DC Voltage and Current Specifications ...........99

7-6 Processor Uncore (V

CCIO

) Supply DC Voltage and Current Specifications.......................101

7-7 Memory Controller (VDDQ) Supply DC Voltage and Current Specifications .................... 101

7-8 System Agent (VCCSA) Supply DC Voltage and Current Specifications .........................101

7-9 Processor PLL (VCCPLL) Supply DC Voltage and Current Specifications......................... 102

7-10 Processor Graphics (VAXG) Supply DC Voltage and Current Specifications .................... 102

7-11 DDR3/DDR3L/DDR3L-RS Signal Group DC Specifications............................................103

7-12 Control Sideband and TAP Signal Group DC Specifications ..........................................104

7-13 PCI Express* DC Specifications...............................................................................105

7-14 eDP DC Specifications ........................................................................................... 105

7-15 PECI DC Electrical Limits........................................................................................107

8-1 rPGA988B Processor Pin List by Pin Name ................................................................ 110

8-2 BGA1224 Processor Ball List by Ball Name ............................................................... 123

8-3 BGA1023 Processor Ball List by Ball Name ............................................................... 142

9-1 DDR Data Swizzling Table – Channel A ....................................................................166

9-2 DDR Data Swizzling Table for Package – Channel B ...................................................167

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 167 168

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HP KC.32101.DMP Datasheet Page 8

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