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DDR Data Swizzling
166 Datasheet, Volume 1
Table 9-1. DDR Data Swizzling
Table – Channel A
Pin Name
Pin
Number
rPGA
Pin
Number
BGA1023
Pin
Number
BGA1224
MC Pin
Name
SA_DQ[0] C5 AG6 AL6 DQ06
SA_DQ[1] D5 AJ6 AL8 DQ05
SA_DQ[2] D3 AP11 AP7 DQ01
SA_DQ[3] D2 AL6 AM5 DQ00
SA_DQ[4] D6 AJ10 AK7 DQ04
SA_DQ[5] C6 AJ8 AL10 DQ07
SA_DQ[6] C2 AL8 AN10 DQ02
SA_DQ[7] C3 AL7 AM9 DQ03
SA_DQ[8] F10 AR11 AR10 DQ15
SA_DQ[9] F8 AP6 AR8 DQ13
SA_DQ[10] G10 AU6 AV7 DQ08
SA_DQ[11] G9 AV9 AY5 DQ09
SA_DQ[12] F9 AR6 AT5 DQ14
SA_DQ[13] F7 AP8 AR6 DQ12
SA_DQ[14] G8 AT13 AW6 DQ10
SA_DQ[15] G7 AU13 AT9 DQ11
SA_DQ[16] K4 BC7 BA6 DQ21
SA_DQ[17] K5 BB7 BA8 DQ19
SA_DQ[18] K1 BA13 BG6 DQ16
SA_DQ[19] J1 BB11 AY9 DQ18
SA_DQ[20] J5 BA7 AW8 DQ23
SA_DQ[21] J4 BA9 BB7 DQ22
SA_DQ[22] J2 BB9 BC8 DQ20
SA_DQ[23] K2 AY13 BE4 DQ17
SA_DQ[24] M8 AV14 AW12 DQ28
SA_DQ[25] N10 AR14 AV11 DQ30
SA_DQ[26] N8 AY17 BB11 DQ24
SA_DQ[27] N7 AR19 BA12 DQ25
SA_DQ[28] M10 BA14 BE8 DQ31
SA_DQ[29] M9 AU14 BA10 DQ29
SA_DQ[30] N9 BB14 BD11 DQ27
SA_DQ[31] M7 BB17 BE12 DQ26
SA_DQ[32] AG6 BA45 BB49 DQ36
SA_DQ[33] AG5 AR43 AY49 DQ39
SA_DQ[34] AK6 AW48 BE52 DQ32
SA_DQ[35] AK5 BC48 BD51 DQ33
SA_DQ[36] AH5 BC45 BD49 DQ38
SA_DQ[37] AH6 AR45 BE48 DQ35
SA_DQ[38]AJ5AT48BA52DQ37
SA_DQ[39] AJ6 AY48 AY51 DQ34
SA_DQ[40] AJ8 BA49 BC54 DQ45
SA_DQ[41] AK8 AV49 AY53 DQ44
SA_DQ[42] AJ9 BB51 AW54 DQ43
SA_DQ[43] AK9 AY53 AY55 DQ41
SA_DQ[44] AH8 BB49 BD53 DQ46
SA_DQ[45] AH9 AU49 BB53 DQ47
SA_DQ[46] AL9 BA53 BE56 DQ40
SA_DQ[47] AL8 BB55 BA56 DQ42
SA_DQ[48] AP11 BA55 BD57 DQ52
SA_DQ[49] AN11 AV56 BF61 DQ53
SA_DQ[50] AL12 AP50 BA60 DQ50
SA_DQ[51] AM12 AP53 BB61 DQ51
SA_DQ[52] AM11 AV54 BE60 DQ54
SA_DQ[53] AL11 AT54 BD63 DQ55
SA_DQ[54] AP12 AP56 BB59 DQ48
SA_DQ[55] AN12 AP52 BC58 DQ49
SA_DQ[56] AJ14 AN57 AW58 DQ61
SA_DQ[57] AH14 AN53 AY59 DQ63
SA_DQ[58] AL15 AG56 AL60 DQ59
SA_DQ[59] AK15 AG53 AP61 DQ58
SA_DQ[60] AL14 AN55 AW60 DQ62
SA_DQ[61] AK14 AN52 AY57 DQ60
SA_DQ[62] AJ15 AG55 AN60 DQ57
SA_DQ[63] AH15 AK56 AR60 DQ56
Table 9-1. DDR Data Swizzling
Table – Channel A
Pin Name
Pin
Number
rPGA
Pin
Number
BGA1023
Pin
Number
BGA1224
MC Pin
Name
- Mobile 3rd Generation Intel 1
- Processor Family 1
- 2 Datasheet, Volume 1 2
- Contents 3
- 4 Datasheet, Volume 1 4
- Datasheet, Volume 1 5 5
- 6 Datasheet, Volume 1 6
- Datasheet, Volume 1 7 7
- 8 Datasheet, Volume 1 8
- Revision History 9
- 10 Datasheet, Volume 1 10
- 1 Introduction 11
- Processor 12
- 1.1 Processor Feature Details 13
- 1.2 Interfaces 13
- 1.2.2 PCI Express* 14
- Datasheet, Volume 1 15 15
- Introduction 15
- 1.2.5 Processor Graphics 16
- 1.3 Power Management Support 17
- Core™ Processor 18
- Family SKU Definition 18
- 1.5 Package 18
- 1.6 Processor Compatibility 19
- 1.7 Terminology 20
- 1.8 Related Documents 22
- 2 Interfaces 23
- 2.1.3.1 Single-Channel Mode 25
- Flex Memory Technology Mode 25
- Interfaces 26
- 26 Datasheet, Volume 1 26
- 2.1.5.2 Command Overlap 27
- 2.2 PCI Express* Interface 28
- 2.2.1.1 Transaction Layer 29
- 2.2.1.2 Data Link Layer 29
- 2.2.1.3 Physical Layer 29
- 30 Datasheet, Volume 1 30
- 2.2.3 PCI Express* Graphics 31
- 2.3.1 DMI Error Flow 32
- 2.3.3 DMI Link Down 32
- Datasheet, Volume 1 33 33
- 2.4.1.2 3D Pipeline 34
- 2.4.1.3 Video Engine 34
- 2.4.1.4 2D Engine 35
- 2.4.2.1 Display Planes 36
- 2.4.2.2 Display Pipes 37
- 2.4.2.3 Display Ports 37
- 2.6 Interface Clocking 38
- 3 Technologies 39
- Technologies 40
- 40 Datasheet, Volume 1 40
- 3.2 Intel 41
- 3.3 Intel 42
- Hyper-Threading Technology 42
- 3.4 Intel 42
- Turbo Boost Technology 42
- 3.4.1 Intel 43
- 3.4.2 Intel 43
- 3.5 Intel 44
- 3.7 Intel 45
- 64 Architecture x2APIC 45
- 46 Datasheet, Volume 1 46
- 4 Power Management 47
- 4.1 ACPI States Supported 48
- 4.1.5 DMI States 49
- 4.2.1 Enhanced Intel 50
- SpeedStep 50
- Technology 50
- 4.2.2 Low-Power Idle States 51
- 4.2.4.1 Core C0 State 53
- 4.2.4.2 Core C1/C1E State 53
- 4.2.4.3 Core C3 State 53
- 4.2.4.4 Core C6 State 53
- 4.2.4.5 Core C7 State 54
- 4.2.4.6 C-State Auto-Demotion 54
- 4.2.5.1 Package C0 56
- 4.2.5.2 Package C1/C1E 56
- 4.2.5.3 Package C3 State 56
- 4.2.5.4 Package C6 State 56
- 4.2.5.5 Package C7 State 57
- 4.3 IMC Power Management 57
- Power Management 58
- 58 Datasheet, Volume 1 58
- Datasheet, Volume 1 59 59
- 4.5 DMI Power Management 61
- 4.6 Graphics Power Management 61
- 62 Datasheet, Volume 1 62
- (SDRRST) 63
- 64 Datasheet, Volume 1 64
- 5 Thermal Management 65
- 5.3 Intel 66
- System Thermal Response Time 67
- 5.3.2 Power Plane Control 68
- 5.3.3 Turbo Time Parameter 68
- 5.4.1 Configurable TDP 68
- Thermal Management 69
- Mode Description 69
- Note Definition 70
- Table 5-3. TDP Specifications 71
- Max Units Notes 72
- Segment Symbol 73
- Idle Parameter Min Typ Max 73
- Units Notes 73
- 5.6.1.1 TCC Activation Offset 74
- 5.6.1.3 Clock Modulation 76
- 78 Datasheet, Volume 1 78
- 5.6.3.5 THERMTRIP# Signal 79
- 80 Datasheet, Volume 1 80
- 6 Signal Description 81
- 6.1 System Memory Interface 82
- Table 6-3. Memory Channel B 83
- 6.6 Intel 85
- Table 6-10. PLL Signals 86
- Table 6-8. Intel 86
- 6.11 Power Sequencing 88
- 6.12 Processor Power Signals 89
- 6.13 Sense Signals 89
- 6.14 Ground and NCTF 90
- 7 Electrical Specifications 91
- 7.4 System Agent (SA) Vcc VID 95
- 7.6 Signal Groups 96
- (Prior to Board Attach) 98
- 7.9 DC Specifications 99
- Table 7-5. Processor Core (V 100
- Electrical Specifications 101
- Table 7-9. Processor PLL (V 102
- ± 200 mV and the 104
- DC Specifications 106
- 108 Datasheet, Volume 1 108
- 8 Processor Pin, Signal, and 109
- Datasheet, Volume 1 121 121
- 122 Datasheet, Volume 1 122
- 140 Datasheet, Volume 1 140
- Datasheet, Volume 1 141 141
- 156 Datasheet, Volume 1 156
- Datasheet, Volume 1 157 157
- 158 Datasheet, Volume 1 158
- Datasheet, Volume 1 159 159
- 160 Datasheet, Volume 1 160
- Datasheet, Volume 1 161 161
- 162 Datasheet, Volume 1 162
- Datasheet, Volume 1 163 163
- 164 Datasheet, Volume 1 164
- 9 DDR Data Swizzling 165
- Table – Channel A 166
- DDR Data Swizzling 168
- 168 Datasheet, Volume 1 168
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