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Introduction
16 Datasheet, Volume 1
• 64-bit downstream address format; however, the processor never generates an
address above 64 GB (Bits 63:36 will always be zeros)
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Supports the following traffic types to or from the PCH:
—DMI -> DRAM
— DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only)
— Processor core -> DMI
• APIC and MSI interrupt messaging support:
— Message Signaled Interrupt (MSI and MSI-X) messages
• Downstream SMI, SCI and SERR error indication
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters
• DC coupling – no capacitors between the processor and the PCH
• Polarity inversion
• PCH end-to-end lane reversal across the link
• Supports Half Swing “low-power/low-voltage”
1.2.4 Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master. The processor supports the PECI 3.0
Specification.
1.2.5 Processor Graphics
• The Processor Graphics contains a refresh of the seventh generation graphics core
enabling substantial gains in performance and lower power consumption. Up to
16
EU support.
• Next Generation Intel Clear Video Technology HD Support is a collection of video
playback and enhancement features that improve the end user’s viewing
experience
— Encode/transcode HD content
— Playback of high definition content including Blu-ray Disc*
— Superior image quality with sharper, more colorful images
— Playback of Blu-ray disc S3D content using HDMI (V.1.4 with 3D)
• DirectX* Video Acceleration (DXVA) support for accelerating video processing
— Full AVC/VC1/MPEG2 HW Decode
• Advanced Scheduler 2.0, 1.0, XPDM support
• Windows* 7, Windows* XP, OSX, Linux OS Support
• DirectX* 11, DirectX* 10.1, DirectX* 10, DirectX* 9 support
• OpenGL* 3.0 support
- Mobile 3rd Generation Intel 1
- Processor Family 1
- 2 Datasheet, Volume 1 2
- Contents 3
- 4 Datasheet, Volume 1 4
- Datasheet, Volume 1 5 5
- 6 Datasheet, Volume 1 6
- Datasheet, Volume 1 7 7
- 8 Datasheet, Volume 1 8
- Revision History 9
- 10 Datasheet, Volume 1 10
- 1 Introduction 11
- Processor 12
- 1.1 Processor Feature Details 13
- 1.2 Interfaces 13
- 1.2.2 PCI Express* 14
- Datasheet, Volume 1 15 15
- Introduction 15
- 1.2.5 Processor Graphics 16
- 1.3 Power Management Support 17
- Core™ Processor 18
- Family SKU Definition 18
- 1.5 Package 18
- 1.6 Processor Compatibility 19
- 1.7 Terminology 20
- 1.8 Related Documents 22
- 2 Interfaces 23
- 2.1.3.1 Single-Channel Mode 25
- Flex Memory Technology Mode 25
- Interfaces 26
- 26 Datasheet, Volume 1 26
- 2.1.5.2 Command Overlap 27
- 2.2 PCI Express* Interface 28
- 2.2.1.1 Transaction Layer 29
- 2.2.1.2 Data Link Layer 29
- 2.2.1.3 Physical Layer 29
- 30 Datasheet, Volume 1 30
- 2.2.3 PCI Express* Graphics 31
- 2.3.1 DMI Error Flow 32
- 2.3.3 DMI Link Down 32
- Datasheet, Volume 1 33 33
- 2.4.1.2 3D Pipeline 34
- 2.4.1.3 Video Engine 34
- 2.4.1.4 2D Engine 35
- 2.4.2.1 Display Planes 36
- 2.4.2.2 Display Pipes 37
- 2.4.2.3 Display Ports 37
- 2.6 Interface Clocking 38
- 3 Technologies 39
- Technologies 40
- 40 Datasheet, Volume 1 40
- 3.2 Intel 41
- 3.3 Intel 42
- Hyper-Threading Technology 42
- 3.4 Intel 42
- Turbo Boost Technology 42
- 3.4.1 Intel 43
- 3.4.2 Intel 43
- 3.5 Intel 44
- 3.7 Intel 45
- 64 Architecture x2APIC 45
- 46 Datasheet, Volume 1 46
- 4 Power Management 47
- 4.1 ACPI States Supported 48
- 4.1.5 DMI States 49
- 4.2.1 Enhanced Intel 50
- SpeedStep 50
- Technology 50
- 4.2.2 Low-Power Idle States 51
- 4.2.4.1 Core C0 State 53
- 4.2.4.2 Core C1/C1E State 53
- 4.2.4.3 Core C3 State 53
- 4.2.4.4 Core C6 State 53
- 4.2.4.5 Core C7 State 54
- 4.2.4.6 C-State Auto-Demotion 54
- 4.2.5.1 Package C0 56
- 4.2.5.2 Package C1/C1E 56
- 4.2.5.3 Package C3 State 56
- 4.2.5.4 Package C6 State 56
- 4.2.5.5 Package C7 State 57
- 4.3 IMC Power Management 57
- Power Management 58
- 58 Datasheet, Volume 1 58
- Datasheet, Volume 1 59 59
- 4.5 DMI Power Management 61
- 4.6 Graphics Power Management 61
- 62 Datasheet, Volume 1 62
- (SDRRST) 63
- 64 Datasheet, Volume 1 64
- 5 Thermal Management 65
- 5.3 Intel 66
- System Thermal Response Time 67
- 5.3.2 Power Plane Control 68
- 5.3.3 Turbo Time Parameter 68
- 5.4.1 Configurable TDP 68
- Thermal Management 69
- Mode Description 69
- Note Definition 70
- Table 5-3. TDP Specifications 71
- Max Units Notes 72
- Segment Symbol 73
- Idle Parameter Min Typ Max 73
- Units Notes 73
- 5.6.1.1 TCC Activation Offset 74
- 5.6.1.3 Clock Modulation 76
- 78 Datasheet, Volume 1 78
- 5.6.3.5 THERMTRIP# Signal 79
- 80 Datasheet, Volume 1 80
- 6 Signal Description 81
- 6.1 System Memory Interface 82
- Table 6-3. Memory Channel B 83
- 6.6 Intel 85
- Table 6-10. PLL Signals 86
- Table 6-8. Intel 86
- 6.11 Power Sequencing 88
- 6.12 Processor Power Signals 89
- 6.13 Sense Signals 89
- 6.14 Ground and NCTF 90
- 7 Electrical Specifications 91
- 7.4 System Agent (SA) Vcc VID 95
- 7.6 Signal Groups 96
- (Prior to Board Attach) 98
- 7.9 DC Specifications 99
- Table 7-5. Processor Core (V 100
- Electrical Specifications 101
- Table 7-9. Processor PLL (V 102
- ± 200 mV and the 104
- DC Specifications 106
- 108 Datasheet, Volume 1 108
- 8 Processor Pin, Signal, and 109
- Datasheet, Volume 1 121 121
- 122 Datasheet, Volume 1 122
- 140 Datasheet, Volume 1 140
- Datasheet, Volume 1 141 141
- 156 Datasheet, Volume 1 156
- Datasheet, Volume 1 157 157
- 158 Datasheet, Volume 1 158
- Datasheet, Volume 1 159 159
- 160 Datasheet, Volume 1 160
- Datasheet, Volume 1 161 161
- 162 Datasheet, Volume 1 162
- Datasheet, Volume 1 163 163
- 164 Datasheet, Volume 1 164
- 9 DDR Data Swizzling 165
- Table – Channel A 166
- DDR Data Swizzling 168
- 168 Datasheet, Volume 1 168
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