HP Integrity rx2600 Specifications Page 20

  • Download
  • Add to my manuals
  • Print
  • Page
    / 30
  • Table of contents
  • BOOKMARKS
  • Rated. / 5. Based on customer reviews
Page view 19
The HP zx1 Chipset is ideal for use with the Intel Itanium 2 processor because it complements the processor’s
price/performance advantages. Moreover, the new zx1 Chipset leverages HP’s co-developer knowledge of the
CPU itself. Indeed, the HP zx1 Chipset was the turn-on vehicle for the Intel Itanium 2 processor in February 2001.
At that time, Itanium 2–based systems with the HP zx1 Chipset were already running HP-UX, Linux, and Microsoft
Windows.
Features and benefits of the HP zx1 Chipset
Feature User benefit
High memory bandwidth, low memory latency Top application performance, faster time to solution
High memory capacity Optimum performance for large models/databases
133 MHz PCI-X Highest-performance I/O adapters
Modularity Family of Intel Itanium processor-based servers and workstations, each
optimized for the right level of cost and scalability
Architectural overview of the HP Integrity rx1600 server
The HP Integrity rx1600 server supports either one or two Low Voltage Intel Itanium 2 processors linked to the
HP zx1 Chipset memory and I/O controller through a 200 MHz, double-pumped 128-bit front-side system bus.
Total bandwidth on the system bus is 6.4 GB/s.
Figure 10. The HP Integrity rx1600 server architecture features Intel Itanium 2 processors and the HP zx1 Chipset
Intel
Itanium 2
processo
r
Intel
Itanium 2
processo
r
6.4 GB/s
DIMM
DIMM
zx1
MIO
DIMM
4.3 GB/s 4.3 GB/s
DIMM
3.5 GB/s
zx1
IOA
zx1
IOA
Out-of-band management: 10/100BT, VGA, RS-232
PCI-X 133 (1 GB/s)
zx1
IOA
zx1
IOA
10/100/1000BT, Ultra320 SCSI
PCI-X 133 (1 GB/s)
zx1
IOA
zx1
IOA
10/100BT, USB, DVD
Memory DIMMs are attached directly to two 266 MHz, 4.3 GB/s memory buses. Combined memory bandwidth
across both buses is 8.5 GB/s. Each bus links up to six double data rate (DDR) DRAM memory DIMMs. Total
system memory capacity is 16 GB, via twelve 8 GB DIMMs.
The I/O architecture consists of seven 0.5 GB/s channels allocated among five zx1 Chipset I/O adapters. Each
of these seven adapters provides a PCI-X or PCI bus to the available I/O slots and core I/O devices. The first four
channels connect to two 133 MHz PCI-X I/O slots, providing 1 GB/s of sustained throughput per slot. These slots
are ideal for high-bandwidth I/O adapters such as high-performance clustering interconnect. The remaining three
20
Page view 19
1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 29 30

Comments to this Manuals

No comments