HP 8-Channel User Manual download pdf (Page 184)

In order to avoid contention and/or invalid data reads, there are certain

rules that must be observed:

1 A controller must not write to any of the RAM registers when

Command/Parameter Ready is false.

2 The DSP must not write to any of the RAM registers when either

Command/Parameter Ready or Query Response Ready is true.

3 A controller must not read any of the RAM registers when Query Response

Ready is false.

4 The DSP must not read any of the RAM registers when Command/Parameter

Ready is true.

5 When writing a command together with parameter, a controller must always

write to the Command Register last.

6 When executing a command that requires it to return response data, the DSP

must set the Query Response Ready bit no later than the

Command/Parameter Ready bit.

7 The DSP must not clear the Done bit while Command/Parameter Ready is

true.

8 The DSP must not change the Err* bit while Done is true.

9 A controller must not regard the done bits a valid while Command/Parameter

Ready is false.

10 A controller must not regard the Err* bit as valid while Done is false.

Controller Protocol Examples

There are three basic procedures used by a controller, Write Command,

Read Response, and Wait for Done. These can be combined for more

complex sequences.

Write Command

This is the procedure to send a command to the DSP.

1 Wait for Command/Parameter Ready true.

2 Write any parameters to the Parameter registers and RAM.

3 Write the command to the Command register.

Read Response

This is the procedure for reading a response to query command.

1 Wait for Query Response Ready true.

2 Read the data from the Query Response register and any additional data from

the Parameter registers and RAM.

HP E1433A User's Guide

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HP 8-Channel User Manual Page 184